Summary

• bind torch/Inductor nested CUDA capture streams to the B12X channel selected by their enclosing graph capture
• keep target and MTP/draft graph managers on distinct PCIe oneshot signal and staging buffers
• apply the same capture ownership model to the PCIe DCP A2A pool
• preserve legacy fallback behavior for captures entered without a pool capture context
• add CPU regression coverage for separate target/draft outer and nested stream pairs in both pools

Root cause

A communication channel owns mutable signal counters and double-buffered IPC staging memory. The old nested-capture fallback selected the first existing channel because allocating during CUDA capture is illegal. Independent target and MTP graph managers could therefore capture one shared channel and replay it concurrently, corrupting its state.

The pools now maintain an enclosing capture-channel stack. A torch/Inductor-owned nested capture stream aliases only the channel selected by its own outer graph manager. Target and draft captures consequently remain isolated without adding a runtime copy or synchronization.

Validation

• tests/distributed/test_pcie_oneshot.py and tests/distributed/test_pcie_dcp_a2a.py: 32 passed
• Ruff and git diff --check: passed
• GLM-5.2 TP6/DCP6/MTP3 with vLLM multichannel wiring survived the previously deterministic CC4 failure for both original and online-MXFP8 configurations

Integration

• Pair with [GG] fix(concurrency): isolate graph state and gate B12X MoE overlap vllm#132, which changes the unsafe oneshot default, right-sizes per-stream buffers, makes DCP A2A multichannel, and enters these pool contexts during graph capture.